Note: Register constant names are preserved from the MC9S12C128V1 reference manual provided by Motorola/FreeScale. While the names of the registers are fairly cryptic mnemonics, they are included this way to facilitate easy reference to the manual. Where possible, the doxygen comment above the description fully defines what the register does, and the meaning of each bit within the register.
Enumerations | |
enum | { TOTAL_TASKS = 5, TOTAL_FEATURES = 30, MODULE_BASE = 0x0000 } |
Variables | |
volatile char *const | PEAR = (volatile char *)MODULE_BASE+0x0A |
PEAR register. | |
volatile char *const | MODE = (volatile char *)MODULE_BASE+0x0B |
MODE register. | |
volatile char *const | PUCR = (volatile char *)MODULE_BASE+0x0C |
Pullup control register. | |
volatile char *const | RDRIV = (volatile char *)MODULE_BASE+0x0D |
RDRIV Register. | |
volatile char *const | EBICTL = (volatile char *)MODULE_BASE+0x0E |
EBICTL Register. | |
volatile char *const | INITRM = (volatile char *)MODULE_BASE+0x10 |
INITRM Register. | |
volatile char *const | INITRG = (volatile char *)MODULE_BASE+0x11 |
INITRG Register. | |
volatile char *const | INITEE = (volatile char *)MODULE_BASE+0x12 |
INITEE Register. | |
volatile char *const | MISC = (volatile char *)MODULE_BASE+0x13 |
MISC Register. | |
volatile char *const | MEMSIZ0 = (volatile char *)MODULE_BASE+0x1C |
MEMSIZ0 Register. | |
volatile char *const | MEMSIZ1 = (volatile char *)MODULE_BASE+0x1D |
MEMSIZ1 Register. | |
volatile char *const | PAGE = (volatile char *)MODULE_BASE+0x30 |
Page control register. | |
volatile char *const | ITCR = (volatile char *)MODULE_BASE+0x15 |
ITCR Register. | |
volatile char *const | ITEST = (volatile char *)MODULE_BASE+0x16 |
ITEST Register. | |
volatile char *const | INTCR = (volatile char *)MODULE_BASE+0x1E |
INTCR Register. | |
volatile char *const | HIPRO = (volatile char *)MODULE_BASE+0x1F |
HIPRO Register. | |
volatile char *const | VREGCTL = (volatile char *)MODULE_BASE+0x19 |
Voltage regulation control 3.3V. | |
volatile char *const | SYNR = (volatile char *)MODULE_BASE+0x34 |
SYNR Register. | |
volatile char *const | REFDV = (volatile char *)MODULE_BASE+0x35 |
REFDV Register. | |
volatile char *const | CRGFLG = (volatile char *)MODULE_BASE+0x37 |
CRGFLG Register. | |
volatile char *const | CRGINT = (volatile char *)MODULE_BASE+0x38 |
CRGINT Register. | |
volatile char *const | CLKSEL = (volatile char *)MODULE_BASE+0x39 |
CLKSEL Register. | |
volatile char *const | PLLCTL = (volatile char *)MODULE_BASE+0x3A |
PLLCTL Register. | |
volatile char *const | RTICTL = (volatile char *)MODULE_BASE+0x3B |
RTICTL Register. | |
volatile char *const | COPCTL = (volatile char *)MODULE_BASE+0x3C |
COPCTL Register. | |
volatile char *const | ARMCOP = (volatile char *)MODULE_BASE+0x3F |
ARMCOP Register. | |
volatile char *const | PARTIDH = (volatile char *)MODULE_BASE+0x1A |
PARTIDH register. | |
volatile char *const | PARTIDL = (volatile char *)MODULE_BASE+0x1B |
PARTIDL register. | |
volatile char *const | ATDCTL0 = (volatile char *)MODULE_BASE+0x80 |
A to D Control Register 0. | |
volatile char *const | ATDCTL1 = (volatile char *)MODULE_BASE+0x81 |
A to D Control Register 1. | |
volatile char *const | ATDCTL2 = (volatile char *)MODULE_BASE+0x82 |
A to D Control Register 2. | |
volatile char *const | ATDCTL3 = (volatile char *)MODULE_BASE+0x83 |
A to D Control Register 3. | |
volatile char *const | ATDCTL4 = (volatile char *)MODULE_BASE+0x84 |
A to D Control Register 4. | |
volatile char *const | ATDCTL5 = (volatile char *)MODULE_BASE+0x85 |
A to D Control Register 5. | |
volatile char *const | ATDSTAT0 = (volatile char *)MODULE_BASE+0x86 |
A to D Status Register 0. | |
volatile char *const | ATDTEST0 = (volatile char *)MODULE_BASE+0x88 |
A to D Test Register 0. | |
volatile char *const | ATDTEST1 = (volatile char *)MODULE_BASE+0x89 |
A to D Test Register 1. | |
volatile char *const | ATDSTAT1 = (volatile char *)MODULE_BASE+0x8B |
A to D Status Register 1. | |
volatile char *const | ATDDIEN = (volatile char *)MODULE_BASE+0x8D |
A to D Interrupt control register. | |
volatile char *const | PORTAD = (volatile char *)MODULE_BASE+0x8F |
A to D Port register. | |
volatile char *const | ATDR0H = (volatile char *)MODULE_BASE+0x90 |
A to D Read register 0 High. | |
volatile char *const | ATDR0L = (volatile char *)MODULE_BASE+0x91 |
A to D Read register 0 Low. | |
volatile char *const | ATDR1H = (volatile char *)MODULE_BASE+0x92 |
A to D Read register 1 High. | |
volatile char *const | ATDR1L = (volatile char *)MODULE_BASE+0x93 |
A to D Read register 1 Low. | |
volatile char *const | ATDR2H = (volatile char *)MODULE_BASE+0x94 |
A to D Read register 2 High. | |
volatile char *const | ATDR2L = (volatile char *)MODULE_BASE+0x95 |
A to D Read register 2 Low. | |
volatile char *const | ATDR3H = (volatile char *)MODULE_BASE+0x96 |
A to D Read register 3 High. | |
volatile char *const | ATDR3L = (volatile char *)MODULE_BASE+0x97 |
A to D Read register 3 Low. | |
volatile char *const | ATDR4H = (volatile char *)MODULE_BASE+0x98 |
A to D Read register 4 High. | |
volatile char *const | ATDR4L = (volatile char *)MODULE_BASE+0x99 |
A to D Read register 4 Low. | |
volatile char *const | ATDR5H = (volatile char *)MODULE_BASE+0x9A |
A to D Read register 5 High. | |
volatile char *const | ATDR5L = (volatile char *)MODULE_BASE+0x9B |
A to D Read register 5 Low. | |
volatile char *const | ATDR6H = (volatile char *)MODULE_BASE+0x9C |
A to D Read register 6 High. | |
volatile char *const | ATDR6L = (volatile char *)MODULE_BASE+0x9D |
A to D Read register 6 Low. | |
volatile char *const | ATDR7H = (volatile char *)MODULE_BASE+0x9E |
A to D Read register 7 High. | |
volatile char *const | ATDR7L = (volatile char *)MODULE_BASE+0x9F |
A to D Read register 7 Low. | |
volatile char *const | SCIBDH = (volatile char *)MODULE_BASE+0xC8 |
Serial Comms High Baud Divisor. | |
volatile char *const | SCIBDL = (volatile char *)MODULE_BASE+0xC9 |
Serial Comms low baud divisor,. | |
volatile char *const | SCICR1 = (volatile char *)MODULE_BASE+0xCA |
Serial Comms Control register 1. | |
volatile char *const | SCICR2 = (volatile char *)MODULE_BASE+0xCB |
SCI Control Register 2. | |
volatile char *const | SCISR1 = (volatile char *)MODULE_BASE+0xCC |
SCI Status Register 1. | |
volatile char *const | SCISR2 = (volatile char *)MODULE_BASE+0xCD |
SCI Status Register 2. | |
volatile char *const | SCIDRH = (volatile char *)MODULE_BASE+0xCE |
SCI Data High Register. | |
volatile char *const | SCIDRL = (volatile char *)MODULE_BASE+0xCF |
SCI Data Low Register. | |
volatile char *const | PORTA = (volatile char *)MODULE_BASE |
Data register General Purpose I/O Port A. | |
volatile char *const | PORTB = (volatile char *)MODULE_BASE+1 |
Data register General Purpose I/O Port B. | |
volatile char *const | DDRA = (volatile char *)MODULE_BASE+2 |
Direction control register Port A. | |
volatile char *const | DDRB = (volatile char *)MODULE_BASE+3 |
Direction control register Port B. | |
volatile char *const | PORTE = (volatile char *)MODULE_BASE+8 |
Data register General Purpose I/O Port E. | |
volatile char *const | DDRE = (volatile char *)MODULE_BASE+9 |
Direction control register Port E. | |
volatile char *const | PORTK = (volatile char *)MODULE_BASE+32 |
Data register General Purpose I/O Port K. | |
volatile char *const | DDRK = (volatile char *)MODULE_BASE+33 |
Direction control register Port K. |
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ARMCOP Register.
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A to D Control Register 0.
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A to D Control Register 1.
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A to D Control Register 2.
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A to D Control Register 3.
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A to D Control Register 4.
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A to D Control Register 5.
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A to D Interrupt control register.
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A to D Read register 0 High.
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A to D Read register 0 Low.
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A to D Read register 1 High.
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A to D Read register 1 Low.
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A to D Read register 2 High.
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A to D Read register 2 Low.
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A to D Read register 3 High.
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A to D Read register 3 Low.
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A to D Read register 4 High.
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A to D Read register 4 Low.
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A to D Read register 5 High.
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A to D Read register 5 Low.
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A to D Read register 6 High.
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A to D Read register 6 Low.
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A to D Read register 7 High.
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A to D Read register 7 Low.
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A to D Status Register 0.
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A to D Status Register 1.
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A to D Test Register 0.
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A to D Test Register 1.
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CLKSEL Register.
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COPCTL Register.
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CRGFLG Register.
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CRGINT Register.
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Direction control register Port A. bit value of 0 sets it to input bit value of 1 sets it to output |
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Direction control register Port B. bit value of 0 sets it to input bit value of 1 sets it to output |
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Direction control register Port E. bit value of 0 sets it to input bit value of 1 sets it to output |
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Direction control register Port K. bit value of 0 sets it to input bit value of 1 sets it to output |
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EBICTL Register.
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HIPRO Register.
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INITEE Register.
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INITRG Register.
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INITRM Register.
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INTCR Register.
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ITCR Register.
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ITEST Register.
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MEMSIZ0 Register.
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MEMSIZ1 Register.
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MISC Register.
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MODE register.
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Page control register.
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PARTIDH register.
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PARTIDL register.
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PEAR register.
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PLLCTL Register.
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Data register General Purpose I/O Port A.
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A to D Port register.
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Data register General Purpose I/O Port B.
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Data register General Purpose I/O Port E.
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Data register General Purpose I/O Port K.
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Pullup control register. (bit 7 {MSB}) - Enable pullup resistors port K (bit 4) - Enable pullup resistors port E. (bit 1) - Enable pullup resistors Port B. (bit 0 {LSB}) - Enable pullup resistors Port A. Other bits are unused and should be set to 0. Setting enable to 0 disables internal pullups for corresponding inputs, setting it to 1 enables internal pullups. Only applies to input configured pins, does not enable pullups for output pins. |
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RDRIV Register.
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REFDV Register.
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RTICTL Register.
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Serial Comms High Baud Divisor. Baud rate is a function of the SCI Module clock. The module clock gets divided by 16 times the value programmed into this register. The 5 Least Significant Bits of the high register are combined with the 8 bits from the low register, providing a baud divisor of between 1 and 8191. SCI Baud Rate = SCI Module Clock / (16 x Baud Divisor). Baud Divisor = ((SCIBDH & 0x1F) << 8) | SCIBDL Note: You must write both the high and low bytes for the register to accept the data (in that order). If you write only the high byte, the baud rate won't be updated until you write the low byte. During this period readbacks will not function correctly. Note2: The baud rate generator is disabled when a 0 is written, or before either RE or TE bits are set in SCICR2. |
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Serial Comms low baud divisor,.
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Serial Comms Control register 1. Bit 7 - Loop Select Bit: enables loop operation. In loop operation, the RXD pin is disconnected from the SCI and the transmitter output is internally connected to the receiver input. Both the transmitter and the receiver must be enabled to use the loop function. 0 Normal operation enabled, 1 Loop operation enabled Note: The receiver input is determined by the RSRC bit. bit 6 - SCI Stop in Wait Mode Bit: disables the SCI in wait mode. 0 SCI enabled in wait mode, 1 SCI disabled in wait mode bit 5 - Receiver Source Bit. When in Loop mode,the RSRC bit determines the source for the receiver shift register. 0 Receiver input internally connected to transmitter output, 1 Receiver input connected externally to transmitter bit 4 - Data Format Mode Bit: determines whether data characters are eight or nine bits long. 0 One start bit, eight data bits, one stop bit; 1 One start bit, nine data bits, one stop bit bit 3 - Wakeup Condition Bit: determines which condition wakes up the SCI: a logic 1 (address mark) in the 3 most signi?cant bit position of a received data character or an idle condition on the RXD. 0 Idle line wakeup, 1 Address mark wakeup. bit 2 - Idle Line Type Bit: determines when the receiver starts counting logic 1s as idle character bits. The counting begins either after the start bit or after the stop bit. If the count begins after the start bit, then a string of logic 1s preceding the stop bit may cause false recognition of an idle character. Beginning the count after the stop bit avoids false idle character recognition, but requires properly synchronized transmissions. 0 Idle character bit count begins after start bit, 1 Idle character bit count begins after stop bit. bit 1 - Parity Enable Bit: enables the parity function. When enabled, the parity function inserts a parity bit in the most significant bit position. 0 Parity function disabled, 1 Parity function enabled bit 0 - Parity Type Bit: determines whether the SCI generates and checks for even parity or odd parity. With even parity, an even number of 1s clears the parity bit and an odd number of 1s sets the parity bit. With odd parity, an odd number of 1s clears the parity bit and an even number of 1s sets the parity bit. 0 Even parity, 1 Odd parity |
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SCI Control Register 2.
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SCI Data High Register.
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SCI Data Low Register.
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SCI Status Register 1.
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SCI Status Register 2.
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SYNR Register.
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Voltage regulation control 3.3V.
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